What Are Registers Register CPU What Is a Computer Register CPU Registers vs Memory Computer Registers Definition Processor Register Failure Register AMD Processor Register Intel Processor
| What Are Registers | Register CPU | What Is a Computer Register | CPU Registers vs Memory | Computer Registers Definition | Processor Register Failure | Register AMD Processor | Register Intel Processor |
| Processor_register | Index_register | Accumulator_(computing) | CS_register | Von_Neumann_architecture | Integer_(computer_science) | Instruction_set | X86-64 | ARM_processor | Register_file | Register_alias_table | Addressing_mode | Quantum_register | Stack_register | SWAR | Status_register | Romcc | Memory_hierarchy | Scalable_Processor_ARChitecture | SIMD |
|This article relies largely or entirely upon a single source. (May 2013)|
In computer architecture, a processor register is a small amount of storage available as part of a CPU or other digital processor. Such registers are (typically) addressed by mechanisms other than main memory and can be accessed more quickly. Almost all computers, load-store architecture or not, load data from a larger memory into registers where it is used for arithmetic, manipulated, or tested, by some machine instruction. Manipulated data is then often stored back in main memory, either by the same instruction or a subsequent one. Modern processors use either static or dynamic RAM as main memory, the latter often being implicitly accessed via one or more cache levels. A common property of computer programs is locality of reference: the same values are often accessed repeatedly and frequently used values held in registers improves performance. This is what makes fast registers (and caches) meaningful.
Processor registers are normally at the top of the memory hierarchy, and provide the fastest way to access data. The term normally refers only to the group of registers that are directly encoded as part of an instruction, as defined by the instruction set. However, modern high performance CPUs often have duplicates of these "architectural registers" in order to improve performance via register renaming, allowing parallel and speculative execution. Modern x86 is perhaps the most well known example of this technique.
Allocating frequently used variables to registers can be critical to a program's performance. This register allocation is either performed by a compiler, in the code generation phase, or manually, by an assembly language programmer.
Registers are normally measured by the number of bits they can hold, for example, an "8-bit register" or a "32-bit register". A processor often contains several kinds of registers, that can be classified accordingly to their content or instructions that operate on them:
Hardware registers are similar, but occur outside CPUs.
The table shows the number of registers of several mainstream architectures. Note that in x86-compatible processors the stack pointer (ESP) is counted as an integer register, even though there are a limited number of instructions that may be used to operate on its contents. Similar caveats apply to most architectures.
x86 FPUs have 8 80-bit stack levels in legacy mode, and at least 8 128-bit XMM registers in SSE modes.
|x86-16||8||8 (if FP present)||8086/8088, 80186/80188, 80286, with 8087, 80187 or 80287 for floating-point; without 8087/80187/80287, no floating-point registers|
|x86-32||8||8 (if FP present)||80386 required 80387 for floating-point; later processors had built-in floating point (hence always had 8 FP registers)|
|Motorola 68k||8 data, 8 address||0|
|Emotion Engine||4||1||Vector processing units are not included as it is off core.|
|IBM/360||16||4 (if FP present)||This applies to S/360's successors, System/370 through System/390; FP was optional in System/360, and always present in S/370 and later|
|z/Architecture||16||16||64-bit version of S/360 and successors|
|Itanium||128||128||And 64 1-bit predicate registers and 8 branch registers. The FP registers are 82 bit.|
|SPARC||31||32||Global register 0 is hardwired to 0. Uses register windows.|
|IBM POWER||32||32||And 1 link and 1 count register.|
|Power Architecture||32||32||And 32 128-bit vector registers, 1 link and 1 count register.|
|IBM Cell SPE||0||1||Each SPE contains a 128-bit, 128-entry unified register file.|
|6502||1||0||6502 only content A (Accumulator) register for main purpose registry store and X,Y and SP register are specific purpose for index only.|
|W65C816S||1||0||65C816 is the 16 bit successor of the 6502. X,Y, D(Direct Page register) and SP register are specific purpose for index only. main accumulator extended to 16 bit (B) while keep 8bit (A) for compatibility and number did not change.|
|ARM 32-bit||15||varies (up to 32)||r15 is the program counter, and not usable as a GPR; r13 is the stack pointer; r8-r14 can be switched out for others (banked) on a processor mode switch.|
|ARM 64-bit||31||32||In addition, register r31 is the stack pointer or hardwired to 0.|
|MIPS||31||32||Register 0 is hardwired to 0.|
|Epiphany||64 (per core)||Each instruction controls whether registers are interpreted as integers or single precision floating point. 16 or 64 cores.|
The number of registers available on a processor and the operations that can be performed using those registers has a significant impact on the efficiency of code generated by optimizing compilers. The Strahler number of an expression tree gives the minimum number of registers required to evaluate that expression tree.